1. Field of the Technology
The present technology relates to high density memory devices, and particularly to memory devices in which multiple levels of memory cells are arranged to provide a three-dimensional (3D) array.
2. Description of Related Art
3D memory devices have been developed in a variety of configurations that include stacks of conductive strips separated by insulating material, and vertical active strips between the stacks. Memory cells including charge storage structures are disposed at interface regions between levels of conductive strips in the stacks and the vertical active strips. In a 3D memory architecture, such as Samsung, pp., 192-193, VLSI Tech. 2009, a word line cut is etched through a stack of conductive strips between adjacent channel poly plugs, and a common source line (CSL) for stacks of conductive strips is then formed by N type implantation into a P type substrate through the word line cut (FIG. 5a). However, the junction profile between the N type implantation and the P type substrate is difficult to control, and the relatively low doping concentration in the implantation tends to increase the resistance of the common source line thus formed.
It is desirable to provide a technology for three-dimensional integrated circuit memory that provides a common source line with lower resistance, and can have improved junction profiles between the common source line and the substrate.